[X86] Improve lowering of v2i64 sign bit tests on pre-sse4.2 targets
authorCraig Topper <craig.topper@intel.com>
Tue, 7 Jan 2020 19:08:45 +0000 (11:08 -0800)
committerCraig Topper <craig.topper@intel.com>
Tue, 7 Jan 2020 19:22:03 +0000 (11:22 -0800)
commitb9376690a011765e35d9ca63abe0e7117985f1ed
tree097a3bb1db943a3e65f1c471f87b2bf868243750
parent2f1e5d934e24c0fa560f43d715b6287cc0d5f0e7
[X86] Improve lowering of v2i64 sign bit tests on pre-sse4.2 targets

Without sse4.2 a v2i64 setlt needs to expand into a pcmpgtd, pcmpeqd, 3 shuffles, and 2 logic ops. But if we're only interested in the sign bit of the i64 elements, we can just use one pcmpgtd and shuffle the odd elements to the even elements.

Differential Revision: https://reviews.llvm.org/D72302
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/bitcast-vector-bool.ll
llvm/test/CodeGen/X86/movmsk-cmp.ll
llvm/test/CodeGen/X86/sadd_sat_vec.ll
llvm/test/CodeGen/X86/ssub_sat_vec.ll
llvm/test/CodeGen/X86/vec_saddo.ll