RISC-V: Fix MEMREMAP_WB for systems with Svpbmt
authorAnup Patel <apatel@ventanamicro.com>
Mon, 14 Nov 2022 09:05:34 +0000 (14:35 +0530)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 8 Dec 2022 23:43:58 +0000 (15:43 -0800)
commitb91676fc16cd384a81e3af52c641aa61985cc231
tree9e4b73c47f49f3cc7d80020d31fcc354c1a51a95
parent9abf2313adc1ca1b6180c508c25f22f9395cc780
RISC-V: Fix MEMREMAP_WB for systems with Svpbmt

Currently, the memremap() called with MEMREMAP_WB maps memory using
the generic ioremap() function which breaks on system with Svpbmt
because memory mapped using _PAGE_IOREMAP page attributes is treated
as strongly-ordered non-cacheable IO memory.

To address this, we implement RISC-V specific arch_memremap_wb()
which maps memory using _PAGE_KERNEL page attributes resulting in
write-back cacheable mapping on systems with Svpbmt.

Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support")
Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221114090536.1662624-2-apatel@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/io.h