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(parent: ce1ed55) | patch
[ARM] Don't form "ands" when it isn't scheduled correctly.
authorEli Friedman <efriedma@quicinc.com>
Fri, 22 Mar 2019 20:49:15 +0000 (20:49 +0000)
committerEli Friedman <efriedma@quicinc.com>
Fri, 22 Mar 2019 20:49:15 +0000 (20:49 +0000)
commitb906bba576e6260d17430114179f09f4cec378f1
treec374e8f5658a2d6777f3511aba0800e814786c7dtree | snapshot
parentce1ed55a4a4a6ec49a7fa4dc411de24147aacab5commit | diff
[ARM] Don't form "ands" when it isn't scheduled correctly.

In r322972/r323136, the iteration here was changed to catch cases at the
beginning of a basic block... but we accidentally deleted an important
safety check.  Restore that check to the way it was.

Fixes https://bugs.llvm.org/show_bug.cgi?id=41116

Differential Revision: https://reviews.llvm.org/D59680

llvm-svn: 356809
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp diff | blob | history
llvm/test/CodeGen/ARM/tst-peephole.mir [new file with mode: 0644] blob
Domain: System / Toolchain;