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ARCv2: barriers
authorVineet Gupta <vgupta@synopsys.com>
Wed, 11 Mar 2015 16:12:37 +0000 (21:42 +0530)
committerVineet Gupta <vgupta@synopsys.com>
Thu, 25 Jun 2015 00:30:17 +0000 (06:00 +0530)
commitb8a033023994c4e59697bb3b16b441b38f258390
tree2a5524af921d907162b1f476537117a02c02a127tree | snapshot
parent470c27e4695add2a4e167467775081870d83185acommit | diff
ARCv2: barriers

ARCv2 based HS38 cores are weakly ordered and thus explicit barriers for
kernel proper.

SMP barrier is provided by DMB instruction which also guarantees local
barrier hence used as backend of smp_*mb() as well as *mb() APIs

Also hookup barriers into MMIO accessors to avoid ordering issues in IO

Cc: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
arch/arc/include/asm/Kbuild diff | blob | history
arch/arc/include/asm/barrier.h [new file with mode: 0644] blob
arch/arc/include/asm/io.h diff | blob | history
Domain: System / Kernel; Licenses: GPL-2.0;