x86: Add new MSRs and MSR bits used for Intel Skylake PMU support
authorAndi Kleen <ak@linux.intel.com>
Sun, 10 May 2015 19:22:41 +0000 (12:22 -0700)
committerIngo Molnar <mingo@kernel.org>
Tue, 4 Aug 2015 08:16:56 +0000 (10:16 +0200)
commitb83ff1c8617aac03a1cf807aafa848fe0f0908f2
tree8796f983a30b38fea50c691f2b53fecaf7a00e22
parenta7b58d211ba18c9175b139e18b68c86a6bcc3c3f
x86: Add new MSRs and MSR bits used for Intel Skylake PMU support

Add new MSRs (LBR_INFO) and some new MSR bits used by the Intel Skylake
PMU driver.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1431285767-27027-4-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/include/asm/msr-index.h
arch/x86/include/asm/perf_event.h