drm/amdgpu: Improve Vega20 XGMI TLB flush workaround
authorFelix Kuehling <Felix.Kuehling@amd.com>
Sat, 18 Jan 2020 01:29:13 +0000 (20:29 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 25 Feb 2020 16:01:57 +0000 (11:01 -0500)
commitb80cd524ac44a29635eec377c6f845b3c321b592
treefa578256b9e5a6ef35966d67f5e3f7824145dfeb
parent82c4ebfa35140a75259eed435134e150ac8e459a
drm/amdgpu: Improve Vega20 XGMI TLB flush workaround

Using a heavy-weight TLB flush once is not sufficient. Concurrent
memory accesses in the same TLB cache line can re-populate TLB entries
from stale texture cache (TC) entries while the heavy-weight TLB
flush is in progress. To fix this race condition, perform another TLB
flush after the heavy-weight one, when TC is known to be clean.

Move the workaround into the low-level TLB flushing functions. This way
they apply to amdgpu as well, and KIQ-based TLB flush only needs to
synchronize once.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: shaoyun liu <shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c