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clk: ingenic: jz4740: Fix gating of UDC clock
authorPaul Cercueil <paul@crapouillou.net>
Fri, 25 Jan 2019 15:34:36 +0000 (12:34 -0300)
committerStephen Boyd <sboyd@kernel.org>
Tue, 5 Feb 2019 21:32:26 +0000 (13:32 -0800)
commitb7e29924a1a628aec60d18651b493fa1601bf944
tree1ff184e0917cf778baee0daa585722c762ef1b34tree | snapshot
parentbfeffd155283772bbe78c6a05dec7c0128ee500ccommit | diff
clk: ingenic: jz4740: Fix gating of UDC clock

The UDC clock is gated when the bit is cleared, not when it is set.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Fixes: 2b555a4b9cae ("clk: ingenic: Add missing flag for UDC clock")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/ingenic/jz4740-cgu.c diff | blob | history
Domain: System / Kernel;