[RISCV] Make scalable vector FMA commutable for register allocation.
authorCraig Topper <craig.topper@sifive.com>
Mon, 8 Feb 2021 17:56:47 +0000 (09:56 -0800)
committerCraig Topper <craig.topper@sifive.com>
Mon, 8 Feb 2021 18:05:33 +0000 (10:05 -0800)
commitb7b4f4cbc3a6d2a3ea49aa47ef600271dc4fb19f
tree09b4f1f8dd51b1e39eddd7001ce0b4712897c5eb
parent04af72c5423eb5ff7c0deba2d08cb46d583bb9d4
[RISCV] Make scalable vector FMA commutable for register allocation.

This adds support for commuting operands and converting between
vfmadd and vfmacc to avoid register copies.

To avoid messing up intrinsic behavior, I've added new pseudo
instructions that have the isCommutable flag set. These pseudos also
force a tail agnostic policy. The intrinsic version still use
the tail undisturbed policy.

For best results it looks like we need to start with fmadd and only
pick fmacc if its beneficial. MachineCSE commutes without contraining
the operands and then commutes back if it didn't help with CSE. So
I've made sure that when the operand choice isn't constrained, we
will keep fmadd for MachineCSE and when it does the second commute,
we get back the original instruction.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D95800
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/test/CodeGen/RISCV/rvv/vfmadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfnmadd-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vfnmsub-sdnode.ll