riscv: mm: dma-noncoherent: nonstandard cache operations support
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Fri, 18 Aug 2023 13:57:20 +0000 (14:57 +0100)
committerPalmer Dabbelt <palmer@rivosinc.com>
Fri, 1 Sep 2023 16:08:57 +0000 (09:08 -0700)
commitb79f300c1fd4bd83b1f827c7a0e043fca7aad73c
tree0d237b4071a4e5b7be07418fd9f9cc253f3b6245
parente021ae7f5145d46ab64cb058cbffda31059f37e5
riscv: mm: dma-noncoherent: nonstandard cache operations support

Introduce support for nonstandard noncoherent systems in the RISC-V
architecture. It enables function pointer support to handle cache
management in such systems.

This patch adds a new configuration option called
"RISCV_NONSTANDARD_CACHE_OPS." This option is a boolean flag that
depends on "RISCV_DMA_NONCOHERENT" and enables the function pointer
support for cache management in nonstandard noncoherent systems.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> #
Link: https://lore.kernel.org/r/20230818135723.80612-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/Kconfig
arch/riscv/include/asm/dma-noncoherent.h [new file with mode: 0644]
arch/riscv/mm/dma-noncoherent.c
arch/riscv/mm/pmem.c