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[X86] Add a DAG combine for turning *_extend_vector_inreg+load into an appropriate...
authorCraig Topper <craig.topper@intel.com>
Tue, 2 Jul 2019 23:20:03 +0000 (23:20 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 2 Jul 2019 23:20:03 +0000 (23:20 +0000)
commitb770d2c9d44672c7cd1b82ac32954179686b9c08
tree88286d4bcda00647b1824545feab612e9f576918tree | snapshot
parentaab3891702024fda3394d9995fdc2f24b82ffa5bcommit | diff
[X86] Add a DAG combine for turning *_extend_vector_inreg+load into an appropriate extload if the load isn't volatile.

Remove the corresponding isel patterns that did the same thing without checking for volatile.

This fixes another variation of PR42079

llvm-svn: 364977
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/lib/Target/X86/X86InstrAVX512.td diff | blob | history
llvm/lib/Target/X86/X86InstrSSE.td diff | blob | history
Domain: System / Toolchain;