fsl_esdhc: Correcting esdhc timeout counter calculation
authorPriyanka Jain <Priyanka.Jain@freescale.com>
Thu, 3 Mar 2011 03:48:56 +0000 (09:18 +0530)
committerKumar Gala <galak@kernel.crashing.org>
Mon, 7 Mar 2011 14:49:28 +0000 (08:49 -0600)
commitb71ea33699bb694964929e2cdced80ef794bde69
treeaadaa4c2e5edd0b040c629286fdf16636c736f9d
parent509e19cab43ba38311749eba5ceebd806116ce38
fsl_esdhc: Correcting esdhc timeout counter calculation

- Timeout counter value is set as DTOCV bits in SYSCTL register
  For counter value set as timeout,
  Timeout period = (2^(timeout + 13)) SD Clock cycles

- As per 4.6.2.2 section of SD Card specification v2.00, host should
  cofigure timeout period value to minimum 0.25 sec.

- Number of SD Clock cycles for 0.25sec should be minimum
(SD Clock/sec * 0.25 sec) SD Clock cycles
= (mmc->tran_speed * 1/4) SD Clock cycles

- Calculating timeout based on
(2^(timeout + 13)) >=  mmc->tran_speed * 1/4
Taking log2 both the sides and rounding up to next power of 2
=> timeout + 13 = log2(mmc->tran_speed/4) + 1

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Acked-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
drivers/mmc/fsl_esdhc.c