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(parent: 132b943) | patch
i965: Fix DP write channel ordering on Sandybridge.
authorEric Anholt <eric@anholt.net>
Thu, 8 Jul 2010 20:16:40 +0000 (13:16 -0700)
committerEric Anholt <eric@anholt.net>
Fri, 20 Aug 2010 23:17:39 +0000 (16:17 -0700)
commitb7004350fac622ce4b45a31773ac7b0c186e66d6
tree71ebd3ec9a36ef538aea62167d7fa9f1d6568cf8tree | snapshot
parent132b9439e287f1febbb49362671743a5b90e303ccommit | diff
i965: Fix DP write channel ordering on Sandybridge.

The SIMD16 message no longer has the goofy interleaved format that
made Compr4 compression necessary before.
src/mesa/drivers/dri/i965/brw_wm_emit.c diff | blob | history
Domain: Graphics System / GL;