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(parent: 1fb7a9f) | patch
clk: renesas: r9a07g044: Add POEG clock and reset entries
authorBiju Das <biju.das.jz@bp.renesas.com>
Tue, 10 May 2022 11:06:53 +0000 (12:06 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 6 Jun 2022 09:13:30 +0000 (11:13 +0200)
commitb6ee0bbf388ab38384f92339aa9a1df15e716cfe
tree080358cffa365d3cf0f196efcb412145c46f6465tree | snapshot
parent1fb7a9fb6295220eb96c490581316b35fce180fecommit | diff
clk: renesas: r9a07g044: Add POEG clock and reset entries

Add POEG clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220510110653.7326-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
Domain: System / Kernel;