[X86][BtVer2] Update the WriteLoad latency.
authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>
Mon, 21 Jan 2019 12:04:10 +0000 (12:04 +0000)
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>
Mon, 21 Jan 2019 12:04:10 +0000 (12:04 +0000)
commitb68dd05c14fc232de9be2d88e4f5e2df9e83bd54
tree54d664074aea95bc8a43b75b113a7d5d21d69417
parent44feb4a87bcfc732e1d926dfa45fdd9b4289b2fe
[X86][BtVer2] Update the WriteLoad latency.

r327630 introduced new write definitions for float/vector loads.
Before that revision, WriteLoad was used by both integer/float (scalar/vector)
load. So, WriteLoad had to conservatively declare a latency to 5cy. That is
because the load-to-use latency for float/vector load is 5cy.

Now that we have dedicated writes for float/vector loads, there is no reason why
we should keep the latency of WriteLoad to 5cy. At the moment, WriteLoad is only
used by scalar integer loads only; we can assume an optimstic 3cy latency for
them.
This patch changes that latency from 5cy to 3cy, and regenerates the affected
scheduling/mca tests.

Differential Revision: https://reviews.llvm.org/D56922

llvm-svn: 351742
13 files changed:
llvm/lib/Target/X86/X86ScheduleBtVer2.td
llvm/test/CodeGen/X86/schedule-x86-64-shld.ll
llvm/test/CodeGen/X86/schedule-x86_32.ll
llvm/test/CodeGen/X86/schedule-x86_64.ll
llvm/test/CodeGen/X86/sse-schedule.ll
llvm/test/CodeGen/X86/sse2-schedule.ll
llvm/test/CodeGen/X86/x87-schedule.ll
llvm/test/tools/llvm-mca/X86/BtVer2/resources-avx1.s
llvm/test/tools/llvm-mca/X86/BtVer2/resources-prefetchw.s
llvm/test/tools/llvm-mca/X86/BtVer2/resources-sse1.s
llvm/test/tools/llvm-mca/X86/BtVer2/resources-sse2.s
llvm/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s
llvm/test/tools/llvm-mca/X86/BtVer2/resources-x87.s