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[clang-format] Fix non-case colons in Verilog case lines
authorsstwcw <f0gukp2nk@protonmail.com>
Sun, 19 Mar 2023 21:32:44 +0000 (21:32 +0000)
committersstwcw <f0gukp2nk@protonmail.com>
Sun, 19 Mar 2023 21:41:14 +0000 (21:41 +0000)
commitb688b58f83ceb48dbe185be95372e45de1d51401
tree97a7b8cea79ec6459465647202940dc809000862tree | snapshot
parent84870c4abbacfb97ca025c9219b724f381611380commit | diff
[clang-format] Fix non-case colons in Verilog case lines

Back in D128714, we should have replaced the old rule about colons when
we added the new one.  Because we didn't, all colons got mistaken as
case colons as long as the line began with `case` or `default`.  Now we
remove the rule that we forgot to remove.

Reviewed By: MyDeveloperDay, rymiel

Differential Revision: https://reviews.llvm.org/D145888
clang/lib/Format/TokenAnnotator.cpp diff | blob | history
clang/unittests/Format/FormatTestVerilog.cpp diff | blob | history
Domain: System / Toolchain;