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(parent: 14d8857) | patch
clk: renesas: r9a07g043: Add TSU clock and reset entry
authorBiju Das <biju.das.jz@bp.renesas.com>
Sun, 1 May 2022 08:34:49 +0000 (09:34 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 5 May 2022 10:10:21 +0000 (12:10 +0200)
commitb67685300478ff768bde0d06a2a664a66223945f
treeb28f9c7aca4533cde60364e45263a5d848451352tree | snapshot
parent14d8857d8266bce49dc4ee0d71e6cd79335d7c8ccommit | diff
clk: renesas: r9a07g043: Add TSU clock and reset entry

Add TSU clock and reset entry to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g043-cpg.c diff | blob | history
Domain: System / Kernel;