R600/SI: Use RegisterOperands to specify which operands can accept immediates
authorTom Stellard <thomas.stellard@amd.com>
Mon, 12 Jan 2015 19:33:18 +0000 (19:33 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Mon, 12 Jan 2015 19:33:18 +0000 (19:33 +0000)
commitb6550529a62a1f47c966f33687a10b2a4dc6885a
treeee5aef6aa74e5a18a4bd642037222a716f0c3da8
parent89b26108b12bf608601049e3b6285192fda2ea47
R600/SI: Use RegisterOperands to specify which operands can accept immediates

There are some operands which can take either immediates or registers
and we were previously using different register class to distinguish
between operands that could take immediates and those that could not.

This patch switches to using RegisterOperands which should simplify the
backend by reducing the number of register classes and also make it
easier to implement the assembler.

llvm-svn: 225662
15 files changed:
llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp
llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
llvm/lib/Target/R600/SIDefines.h
llvm/lib/Target/R600/SIISelLowering.cpp
llvm/lib/Target/R600/SIInstrInfo.cpp
llvm/lib/Target/R600/SIInstrInfo.td
llvm/lib/Target/R600/SIRegisterInfo.cpp
llvm/lib/Target/R600/SIRegisterInfo.h
llvm/lib/Target/R600/SIRegisterInfo.td
llvm/test/CodeGen/R600/srl.ll
llvm/test/CodeGen/R600/sub.ll
llvm/test/CodeGen/R600/udivrem.ll
llvm/test/CodeGen/R600/usubo.ll
llvm/test/CodeGen/R600/xor.ll