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[RISCV] Lower experimental_get_vector_length intrinsic to vsetvli for some cases.
authorCraig Topper <craig.topper@sifive.com>
Mon, 5 Jun 2023 22:02:11 +0000 (15:02 -0700)
committerCraig Topper <craig.topper@sifive.com>
Mon, 5 Jun 2023 22:02:11 +0000 (15:02 -0700)
commitb64ddae8a294605819470ce2f8d8b4751d0ffe12
tree0e629b0991c275b46e9e3d2e9b60329d7ac9788ctree | snapshot
parent86b6ac5d54d7fe5cd21beff64b5c2194b1368bdfcommit | diff
[RISCV] Lower experimental_get_vector_length intrinsic to vsetvli for some cases.

This patch lowers to vsetvli when the AVL is i32 or XLenVT and
the VF is a power of 2 in the range [1, 64]. VLEN=32 is not supported
as we don't have a valid type mapping for that. VF=1 is not supported
with Zve32* only.

The element width is used to set the SEW for the vsetvli if possible.
Otherwise we use SEW=8.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D150824
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVISelLowering.h diff | blob | history
llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll diff | blob | history
Domain: System / Toolchain;