[X86][Costmodel] Load/store i32/f32 Stride=4 VF=2 interleaving costs
authorRoman Lebedev <lebedev.ri@gmail.com>
Mon, 4 Oct 2021 16:30:00 +0000 (19:30 +0300)
committerRoman Lebedev <lebedev.ri@gmail.com>
Tue, 5 Oct 2021 13:58:56 +0000 (16:58 +0300)
commitb6234c1edffc8286815c61887eb02fd6ddab0090
tree8c1afe10b4077dd6a3788ca47e800355b903c695
parent095c48fdf3d27a4f346f8680d1d7e89449bb557b
[X86][Costmodel] Load/store i32/f32 Stride=4 VF=2 interleaving costs

Finally, we are getting to the heavy-hitter stuff!

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/7crGWoar6 - for intels `Block RThroughput: =4.0`; for ryzens, `Block RThroughput: <=2.0`
So could pick cost of `4`.

For store we have:
https://godbolt.org/z/T8aq3MszM - for intels `Block RThroughput: =5.0`; for ryzens, `Block RThroughput: <=2.0`
So we could pick cost of `5`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D111060
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll