clk: imx7d: Fix the DDR PLL enable bit
authorFabio Estevam <fabio.estevam@nxp.com>
Tue, 6 Jun 2017 15:45:54 +0000 (12:45 -0300)
committerStephen Boyd <sboyd@codeaurora.org>
Wed, 7 Jun 2017 00:42:41 +0000 (17:42 -0700)
commitb608a89221b401d7b07a1b6330777a034d204410
treeaf312909fcc2f3eece898d1b098fb08c4738d16a
parent4a5f06a01cfd1f7a9141bdb760bf5b68cca7f224
clk: imx7d: Fix the DDR PLL enable bit

Commit ad14972422899b6 ("clk: imx7d: Fix the powerdown bit location
of PLL DDR") used the incorrect bit for the IMX_PLLV3_DDR_IMX7 case.

Fix it accordingly to avoid a kernel hang.

Reported-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/imx/clk-pllv3.c