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(parent: d821ac1) | patch
Add additional operations that masked instructions can combine with
authorNoah Goldstein <goldstein.w.n@gmail.com>
Sun, 26 Feb 2023 17:25:59 +0000 (11:25 -0600)
committerNoah Goldstein <goldstein.w.n@gmail.com>
Sun, 26 Feb 2023 18:11:16 +0000 (12:11 -0600)
commitb5fc2a474ebabb082f52f43cea2d5b299f28bd70
treeca6759a46615c483ee8e07e5a91dd88d824d7936tree | snapshot
parentd821ac1aaf94091c03314c8ba03d6b64c0309038commit | diff
Add additional operations that masked instructions can combine with

Added: OR, SMAX, SMIN, UMAX, UMIN, ABS, SHL, SRL, SRA, MUL

Intentionally not generically using TLI.isBinOp as that causes
regressions as there are many binops that cannot combine with masked
instructions.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D143860
llvm/lib/Target/X86/X86ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/X86/combine-mask-with-shuffle.ll diff | blob | history
llvm/test/CodeGen/X86/vselect-avx512.ll diff | blob | history
Domain: System / Toolchain;