[Hexagon] Adding combine reg, reg with predicated forms.
authorColin LeMahieu <colinl@codeaurora.org>
Mon, 8 Dec 2014 17:33:06 +0000 (17:33 +0000)
committerColin LeMahieu <colinl@codeaurora.org>
Mon, 8 Dec 2014 17:33:06 +0000 (17:33 +0000)
commitb56e6cd9b9bdd0fab494da1d0aa474b8c31c2a73
tree2fa7a5f56b070d7a9d7041864e26239e4b0a431d
parentbc0184464141e0022bb2a1d39b20c48f114bdf2b
[Hexagon] Adding combine reg, reg with predicated forms.

llvm-svn: 223667
llvm/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/test/MC/Disassembler/Hexagon/alu32_perm.txt
llvm/test/MC/Disassembler/Hexagon/alu32_pred.txt