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[VTA][TSIM] Use Module instead of RawModule for testbench by creating an empty bundle...
authorLuis Vega <vegaluisjose@users.noreply.github.com>
Tue, 28 May 2019 04:29:55 +0000 (21:29 -0700)
committerJared Roesch <roeschinc@gmail.com>
Tue, 28 May 2019 04:29:55 +0000 (21:29 -0700)
commitb5507d4546c0714c57f11b93d887edafb3739e94
treea5580250e0934dad61b563e1b96826697ad74195tree | snapshot
parentc0afc91884c1e664e19ab10f5f4898425975a756commit | diff
[VTA][TSIM] Use Module instead of RawModule for testbench by creating an empty bundle for the IO (#3242)

* use Module instead of RawModule for testbench by creating an empty bundle for the IO

* change default back to verilog
vta/apps/tsim_example/hardware/chisel/src/test/scala/dut/TestAccel.scala diff | blob | history
Domain: Machine Learning / ML Framework;