ARM: mm: remove IPI broadcasting on ASID rollover
authorWill Deacon <will.deacon@arm.com>
Fri, 15 Jun 2012 13:47:31 +0000 (14:47 +0100)
committerWill Deacon <will.deacon@arm.com>
Mon, 5 Nov 2012 16:25:25 +0000 (16:25 +0000)
commitb5466f8728527a05a493cc4abe9e6f034a1bbaab
tree26c49a9c00e0e853c5fe1e4366b6af2335f52a95
parent3d70f8c617a436c7146ecb81df2265b4626dfe89
ARM: mm: remove IPI broadcasting on ASID rollover

ASIDs are allocated to MMU contexts based on a rolling counter. This
means that after 255 allocations we must invalidate all existing ASIDs
via an expensive IPI mechanism to synchronise all of the online CPUs and
ensure that all tasks execute with an ASID from the new generation.

This patch changes the rollover behaviour so that we rely instead on the
hardware broadcasting of the TLB invalidation to avoid the IPI calls.
This works by keeping track of the active ASID on each core, which is
then reserved in the case of a rollover so that currently scheduled
tasks can continue to run. For cores without hardware TLB broadcasting,
we keep track of pending flushes in a cpumask, so cores can flush their
local TLB before scheduling a new mm.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
arch/arm/include/asm/mmu.h
arch/arm/include/asm/mmu_context.h
arch/arm/mm/context.c