RISC-V: Add basic support for the Ventana-VT1 core

RISC-V: Add basic support for the Ventana-VT1 core

The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and
XVentanaCondOps.
This introduces a placeholder -mcpu=ventana-vt1, so tooling and
scripts don't need to change once full support (pipeline, tuning,
etc.) will become public later.

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_TUNE): Add ventana-vt1.
	(RISCV_CORE): Ditto.
	* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Ditto.
	* config/riscv/riscv.cc: Add tune_info for ventana-vt1.
	* doc/invoke.texi: Document -mcpu= and -mtune with ventana-vt1.