projects / platform / kernel / linux-starfive.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 4012ab1) | patch
arm64: tegra: Fix SOR powergate clocks and reset
authorSowjanya Komatineni <skomatineni@nvidia.com>
Tue, 5 May 2020 02:31:52 +0000 (19:31 -0700)
committerThierry Reding <treding@nvidia.com>
Wed, 20 May 2020 13:26:09 +0000 (15:26 +0200)
commitb4f99176a501ac34c7f5c9322910e248a2f43397
tree66287ece150a924027ff7e8fe446ad753bebd532tree | snapshot
parent4012ab12b3cbd3efbd7254f04de40903c624a237commit | diff
arm64: tegra: Fix SOR powergate clocks and reset

Tegra210 device tree lists CSI clock and reset under SOR powergate
node.

But Tegra210 has CSICIL in SOR partition and CSI in VENC partition.

So, this patch includes fix for SOR powergate node.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm64/boot/dts/nvidia/tegra210.dtsi diff | blob | history
Domain: System / Kernel;