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(parent: 91f62f0) | patch
[AArch64] Improve codegen for shifted mask op
authorchenglin.bi <chenglin.bi@linaro.org>
Wed, 2 Nov 2022 05:11:35 +0000 (13:11 +0800)
committerchenglin.bi <chenglin.bi@linaro.org>
Wed, 2 Nov 2022 05:11:48 +0000 (13:11 +0800)
commitb4e1466c35d3ca3e04244e8e8b4ffaf0784d6d37
tree7c3bb1a31d429aa54bbbe7100e14b455152fa88etree | snapshot
parent91f62f0e352a4f5c755f1cbec6f27e40a60ff109commit | diff
[AArch64] Improve codegen for shifted mask op

The special case for bit extraction pattern is  `((x >> C) & mask) << C`.
It can be combined to `x & (mask << C)` by return true in isDesirableToCommuteWithShift.

Fix: #56427

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D136014
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/shift-logic.ll diff | blob | history
Domain: System / Toolchain;