ARM & AArch64: make use of common cmpxchg idioms after expansion
authorTim Northover <tnorthover@apple.com>
Fri, 30 May 2014 10:09:59 +0000 (10:09 +0000)
committerTim Northover <tnorthover@apple.com>
Fri, 30 May 2014 10:09:59 +0000 (10:09 +0000)
commitb4ddc0845ab5260023e9afa3f7bc71a0bc731ae6
tree37a8539f9db4739dd57e7bdf39433594e822e2ec
parent5070c18928e4b4855202ee327f537c7a1969051e
ARM & AArch64: make use of common cmpxchg idioms after expansion

The C and C++ semantics for compare_exchange require it to return a bool
indicating success. This gets mapped to LLVM IR which follows each cmpxchg with
an icmp of the value loaded against the desired value.

When lowered to ldxr/stxr loops, this extra comparison is redundant: its
results are implicit in the control-flow of the function.

This commit makes two changes: it replaces that icmp with appropriate PHI
nodes, and then makes sure earlyCSE is called after expansion to actually make
use of the opportunities revealed.

I've also added -{arm,aarch64}-enable-atomic-tidy options, so that
existing fragile tests aren't perturbed too much by the change. Many
of them either rely on undef/unreachable too pervasively to be
restored to something well-defined (particularly while making sure
they test the same obscure assert from many years ago), or depend on a
particular CFG shape, which is disrupted by SimplifyCFG.

rdar://problem/16227836

llvm-svn: 209883
59 files changed:
llvm/lib/CodeGen/AtomicExpandLoadLinkedPass.cpp
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/lib/Target/ARM/ARMTargetMachine.cpp
llvm/test/CodeGen/AArch64/addsub_ext.ll
llvm/test/CodeGen/AArch64/arm64-ands-bad-peephole.ll
llvm/test/CodeGen/AArch64/arm64-cse.ll
llvm/test/CodeGen/AArch64/arm64-early-ifcvt.ll
llvm/test/CodeGen/AArch64/arm64-fp128.ll
llvm/test/CodeGen/AArch64/arm64-frame-index.ll
llvm/test/CodeGen/AArch64/arm64-xaluo.ll
llvm/test/CodeGen/AArch64/atomic-ops.ll
llvm/test/CodeGen/AArch64/blockaddress.ll
llvm/test/CodeGen/AArch64/breg.ll
llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll [new file with mode: 0644]
llvm/test/CodeGen/AArch64/directcond.ll
llvm/test/CodeGen/AArch64/flags-multiuse.ll
llvm/test/CodeGen/AArch64/jump-table.ll
llvm/test/CodeGen/AArch64/ldst-opt.ll
llvm/test/CodeGen/AArch64/tst-br.ll
llvm/test/CodeGen/ARM/2009-11-02-NegativeLane.ll
llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
llvm/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll
llvm/test/CodeGen/ARM/2011-02-04-AntidepMultidef.ll
llvm/test/CodeGen/ARM/2012-11-14-subs_carry.ll
llvm/test/CodeGen/ARM/2013-07-29-vector-or-combine.ll
llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
llvm/test/CodeGen/ARM/atomic-64bit.ll
llvm/test/CodeGen/ARM/call-tc.ll
llvm/test/CodeGen/ARM/cmpxchg-idioms.ll [new file with mode: 0644]
llvm/test/CodeGen/ARM/data-in-code-annotations.ll
llvm/test/CodeGen/ARM/fptoint.ll
llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll
llvm/test/CodeGen/ARM/ifcvt10.ll
llvm/test/CodeGen/ARM/indirectbr-3.ll
llvm/test/CodeGen/ARM/lsr-unfolded-offset.ll
llvm/test/CodeGen/ARM/misched-copy-arm.ll
llvm/test/CodeGen/ARM/reg_sequence.ll
llvm/test/CodeGen/ARM/spill-q.ll
llvm/test/CodeGen/ARM/struct-byval-frame-index.ll
llvm/test/CodeGen/ARM/twoaddrinstr.ll
llvm/test/CodeGen/ARM/vldm-sched-a9.ll
llvm/test/CodeGen/Thumb2/2009-08-01-WrongLDRBOpc.ll
llvm/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll
llvm/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
llvm/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll
llvm/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
llvm/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
llvm/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll
llvm/test/CodeGen/Thumb2/buildvector-crash.ll
llvm/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
llvm/test/CodeGen/Thumb2/ldr-str-imm12.ll
llvm/test/CodeGen/Thumb2/thumb2-branch.ll
llvm/test/CodeGen/Thumb2/thumb2-cbnz.ll
llvm/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
llvm/test/CodeGen/Thumb2/thumb2-ifcvt3.ll
llvm/test/CodeGen/Thumb2/thumb2-spill-q.ll
llvm/test/CodeGen/Thumb2/v8_IT_3.ll
llvm/test/CodeGen/Thumb2/v8_IT_5.ll
llvm/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll