net: phy: icplus: Use the RGMII interface mode to configure clock delays
authorStuart Menefy <stuart.menefy@st.com>
Wed, 23 Jan 2013 00:22:36 +0000 (00:22 +0000)
committerDavid S. Miller <davem@davemloft.net>
Mon, 28 Jan 2013 05:08:22 +0000 (00:08 -0500)
commitb4a496319f2fe4b46d7a9ab246f4fbf23a5a3106
tree92c5897525edea4cff24a42f16b4be3f6a00151d
parent5465740ace36f179de5bb0ccb5d46ddeb945e309
net: phy: icplus: Use the RGMII interface mode to configure clock delays

Like several other PHY devices which support RGMII, the IC+1001 allows
additional delays to by added to the RX_CLK and TX_CLK signals to
compensate for skew between the clock and data signals. Previously this
was always enabled, but this change makes use of the different RGMII
interface modes to allow the user to specify whether this should be
enabled.

Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/phy/icplus.c