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(parent: 7532c98) | patch
ARM: dts: imx6q-b850v3: Update display clock source
authorAkshay Bhat <akshay.bhat@timesys.com>
Mon, 18 Apr 2016 21:19:44 +0000 (17:19 -0400)
committerShawn Guo <shawnguo@kernel.org>
Tue, 26 Apr 2016 03:05:30 +0000 (11:05 +0800)
commitb492b8744da9b205b9b303b111a138b16d56e712
treea5f5917a3a7303f3d56f5fe20f4cfd023d8e37cbtree | snapshot
parent7532c98f3ac212ca1f19be7e628356247b616c74commit | diff
ARM: dts: imx6q-b850v3: Update display clock source

The default monitor that ships with B850v3 requires a 65MHz pixel clock.
65MHz can not be achieved using PLL3 (480MHz/7=68.5MHz). Hence set the
LDB_DIx clock source to PLL5. Since PLL5 is already in use by IPU1_DIx,
set the clock source for IPU1_DIx to PLL2_PFD2 to allow simultaneous
display on both LVDS and HDMI interface.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6q-b850v3.dts diff | blob | history
Domain: System / Kernel;