clk: tm2: update pcie pll parameters [1/1]

clk: tm2: update pcie pll parameters [1/1]

PD#SWPL-5636

Problem:
pcie pll works not well

Solution:
update pcie pll parameters which are provided by vlsi,
do not set M/N/OD/frac registers after the parameters
are setted.

Verify:
test passed on tm2 ab311

Change-Id: I76d64e7ed06c36da3a781ab4d5d79b4b736f2057
Signed-off-by: Jian Hu <jian.hu@amlogic.com>