[AMDGPU] Introduce SIInstrWorklist to process instructions in moveToVALU
authorskc7 <Krishna.Sankisa@amd.com>
Tue, 28 Mar 2023 18:05:02 +0000 (23:35 +0530)
committerskc7 <Krishna.Sankisa@amd.com>
Mon, 10 Apr 2023 06:04:14 +0000 (11:34 +0530)
commitb434051dc83d77c8e8e349ab1992dcb0c795a7ea
treeddd0f80a82baa0d7e9ae6df51a3c9cfa51905c9c
parentd65720652dd644483530ecb547365a2239a97979
[AMDGPU] Introduce SIInstrWorklist to process instructions in moveToVALU

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D147168
29 files changed:
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/test/CodeGen/AMDGPU/add3.ll
llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
llvm/test/CodeGen/AMDGPU/carryout-selection.ll
llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
llvm/test/CodeGen/AMDGPU/ds_read2.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sbfe.ll
llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
llvm/test/CodeGen/AMDGPU/mul.ll
llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir
llvm/test/CodeGen/AMDGPU/sdiv.ll
llvm/test/CodeGen/AMDGPU/sdiv64.ll
llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
llvm/test/CodeGen/AMDGPU/shl.ll
llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
llvm/test/CodeGen/AMDGPU/sra.ll
llvm/test/CodeGen/AMDGPU/srem64.ll
llvm/test/CodeGen/AMDGPU/srl.ll
llvm/test/CodeGen/AMDGPU/sub.ll
llvm/test/CodeGen/AMDGPU/udiv.ll
llvm/test/CodeGen/AMDGPU/udiv64.ll
llvm/test/CodeGen/AMDGPU/udivrem.ll
llvm/test/CodeGen/AMDGPU/urem64.ll
llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll