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(parent: 1791b1f) | patch
imx: mx6q DDR3 init: Fix MR0.PPD
authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Wed, 30 Jan 2013 11:19:17 +0000 (11:19 +0000)
committerStefano Babic <sbabic@denx.de>
Tue, 12 Feb 2013 12:52:31 +0000 (13:52 +0100)
commitb42b5b7a243ab3923fd80ab03f950f036b6e1329
tree2dec05cd0a9861dd8732da17cc05bc843c2c7765tree | snapshot
parent1791b1f97f71bb4f110ca851ab10479640b7bc05commit | diff
imx: mx6q DDR3 init: Fix MR0.PPD

MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which
is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg diff | blob | history
Domain: System / Kernel;