i965/gen6: Force tile alignment for each stencil/hiz LOD
authorJordan Justen <jordan.l.justen@intel.com>
Wed, 28 May 2014 17:36:44 +0000 (10:36 -0700)
committerJordan Justen <jordan.l.justen@intel.com>
Sat, 16 Aug 2014 03:11:42 +0000 (20:11 -0700)
commitb3d68d5a30ac6964aefff65846e28d20af16c345
treec0c0aa618abe3586a10bf71075ac00c0487eb2ce
parent6345a94a9b134b1321b3b290bacde228b12af415
i965/gen6: Force tile alignment for each stencil/hiz LOD

Gen6 doesn't support multiple miplevels for hiz and stencil.

Therefore, we must point to the LOD directly during rendering.

But, we also have removed the tile offsets from normal depth surfaces,
so we need to align each LOD to a tile boundary for hiz and stencil.

v3:
 * Use new array_layout enum

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_tex_layout.c