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(parent: 9783c0d) | patch
clk: mediatek: Fix PLL registers setting flow
authorJames Liao <jamesjj.liao@mediatek.com>
Fri, 10 Jul 2015 08:39:32 +0000 (16:39 +0800)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 28 Jul 2015 18:58:52 +0000 (11:58 -0700)
commitb3be457e5854e3095cd0be850058c765aaf467ab
tree427efcbd2d64d3d21b2642289c89f4e6b3142bc3tree | snapshot
parent9783c0d98501aa146ff467916ab4b8830a655d7ccommit | diff
clk: mediatek: Fix PLL registers setting flow

Write postdiv and pcw settings at the same time for PLLs if postdiv
and pcw settings are on the same register.

This is need by PLLs such as MT8173 MMPLL and ARM*PLL.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/mediatek/clk-pll.c diff | blob | history
Domain: System / Kernel;