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[X86] Model ADC/SBB with immediate 0 more accurately in the Haswell scheduler model
authorCraig Topper <craig.topper@intel.com>
Thu, 7 Mar 2019 21:22:51 +0000 (21:22 +0000)
committerCraig Topper <craig.topper@intel.com>
Thu, 7 Mar 2019 21:22:51 +0000 (21:22 +0000)
commitb3af5d3e57107a3bffe4c2d38b22ae96cee52245
treebcc77d1a4dad0b1279617c73665ae553bee1cd8atree | snapshot
parent4e467043fbb5fc9c7c426019c40f9db85d84f31fcommit | diff
[X86] Model ADC/SBB with immediate 0 more accurately in the Haswell scheduler model

Haswell and possibly Sandybridge have an optimization for ADC/SBB with immediate 0 to use a single uop flow. This only applies GR16/GR32/GR64 with an 8-bit immediate. It does not apply to GR8. It also does not apply to the implicit AX/EAX/RAX forms.

Differential Revision: https://reviews.llvm.org/D59058

llvm-svn: 355635
llvm/lib/Target/X86/X86SchedHaswell.td diff | blob | history
llvm/test/tools/llvm-mca/X86/Haswell/resources-x86_64.s diff | blob | history
Domain: System / Toolchain;