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[RISCV] Fix bug where C_ADDI_HINT_IMM_ZERO was incorrectly disassembled as C_ADDI.
authorCraig Topper <craig.topper@sifive.com>
Sun, 5 Feb 2023 20:31:36 +0000 (12:31 -0800)
committerCraig Topper <craig.topper@sifive.com>
Sun, 5 Feb 2023 20:31:36 +0000 (12:31 -0800)
commitb3ab26b4aa2fe242218b1c0cfae9420f2c4021fa
tree68ae1e680e04cf7f88624bb898ed2fb0caab4567tree | snapshot
parentdd0caa82de593f080469c772b5b092e1bf7f7cc0commit | diff
[RISCV] Fix bug where C_ADDI_HINT_IMM_ZERO was incorrectly disassembled as C_ADDI.

And was then printed as 'mv'.
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp diff | blob | history
llvm/lib/Target/RISCV/RISCVInstrInfoC.td diff | blob | history
llvm/test/MC/RISCV/rvc-hints-valid.s diff | blob | history
Domain: System / Toolchain;