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(parent: ef4cf5a) | patch
rockchip: clk: Add rk3328 SARADC clock support
authorDavid Wu <david.wu@rock-chips.com>
Wed, 20 Sep 2017 06:35:44 +0000 (14:35 +0800)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Sat, 30 Sep 2017 22:33:30 +0000 (00:33 +0200)
commitb375d84135e26d5ec5034a515af4df5981785f37
treedb6f8ccbfbd9a202615b86275432e782d3e16fb1tree | snapshot
parentef4cf5ae393e4adf532f536d6da97c87f88db230commit | diff
rockchip: clk: Add rk3328 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
drivers/clk/rockchip/clk_rk3328.c diff | blob | history
Domain: System / Kernel;