intel: enable L3 cache
authorChia-I Wu <olv@lunarg.com>
Fri, 27 Feb 2015 16:51:16 +0000 (09:51 -0700)
committerChia-I Wu <olv@lunarg.com>
Fri, 27 Feb 2015 19:31:17 +0000 (12:31 -0700)
commitb368698d94b84a963094895bbeddbeeee3e6520f
tree9c10d57f85ae8cbdc82491e3f5984fd78baaa284
parent1b293966226bc7fb6a1e31c3c74a9e461598efe5
intel: enable L3 cache

Set GEN7_MOCS_L3_ON everywhere.
icd/intel/cmd_pipeline.c
icd/intel/view.c