[ARM] Masked loads and stores
authorDavid Green <david.green@arm.com>
Sun, 15 Sep 2019 14:14:47 +0000 (14:14 +0000)
committerDavid Green <david.green@arm.com>
Sun, 15 Sep 2019 14:14:47 +0000 (14:14 +0000)
commitb325c057322ce14b5c561d8ac49508adab7649e5
tree61afc1dbb9a328634e30c70be0261320a0fdc36d
parentb6a0faaa0c793aede7911be241b1895a9ebea41c
[ARM] Masked loads and stores

Masked loads and store fit naturally with MVE, the instructions being easily
predicated. This adds lowering for the simple cases of masked loads and stores.
It does not yet deal with widening/narrowing or pre/post inc, and so is
currently behind an option.

The llvm masked load intrinsic will accept a "passthru" value, dictating the
values used for the zero masked lanes. In MVE the instructions write 0 to the
zero predicated lanes, so we need to match a passthru that isn't 0 (or undef)
with a select instruction to pull in the correct data after the load.

Differential Revision: https://reviews.llvm.org/D67186

llvm-svn: 371932
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMInstrMVE.td
llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
llvm/lib/Target/ARM/ARMTargetTransformInfo.h
llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll
llvm/test/CodeGen/Thumb2/mve-masked-load.ll
llvm/test/CodeGen/Thumb2/mve-masked-store.ll
llvm/test/Transforms/LoopVectorize/ARM/mve-maskedldst.ll [new file with mode: 0644]