drm/i915/dp: BDW cdclk fix for DP audio
authorDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Tue, 1 Nov 2016 18:47:59 +0000 (11:47 -0700)
committerJani Nikula <jani.nikula@intel.com>
Fri, 4 Nov 2016 15:31:09 +0000 (17:31 +0200)
commitb30ce9e0552aa017ac6f2243f3c2d8e36fe52e69
tree2df4ae54fee9913133292cd1a21b4c0b9dae293c
parent2c3a3f44dc13a7c964e93385e1c1ca848656bed0
drm/i915/dp: BDW cdclk fix for DP audio

According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
cycling on/off.

From BSpec:
"Display» BDW-SKL» dpr» [Register] DP_TP_CTL [BDW+,EXCLUDE(CHV)]
Workaround : Do not use DisplayPort with CDCLK less than 432 MHz, audio
enabled, port width x4, and link rate HBR2 (5.4 GHz), or else there may
be audio corruption or screen corruption."

Since, some DP configurations (e.g., MST) use port width x4 and HBR2
link rate, let's increase the cdclk to >= 432 MHz to enable audio for those
cases.

v4: Changed commit message
v3: Combine BDW pixel rate adjustments into a function (Jani)
v2: Restrict fix to BDW
    Retain the set cdclk across modesets (Ville)
Cc: stable@vger.kernel.org
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1478026080-2925-1-git-send-email-dhinakaran.pandiyan@intel.com
drivers/gpu/drm/i915/intel_display.c