projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 9ac548e) | patch
[RISCV] isel (shl (and X, C2), C) -> (slli (srliw X, C3), C3+C).
authorCraig Topper <craig.topper@sifive.com>
Sat, 2 Jul 2022 07:57:35 +0000 (00:57 -0700)
committerCraig Topper <craig.topper@sifive.com>
Sat, 2 Jul 2022 08:04:44 +0000 (01:04 -0700)
commitb2e9684fe4d10dbdd7679a29c6f971dc59ede3dd
treee8926176595835d0f7e310469db02f9fa9c55fa8tree | snapshot
parent9ac548e1181c4d4fea49e312396b5b8c28c316b9commit | diff
[RISCV] isel (shl (and X, C2), C) -> (slli (srliw X, C3), C3+C).

where C2 has 32 leading zeros and C3 trailing zeros.

When the shl is used by an add C is 1,2 or 3, we end up matching
(add (shl X, C), Y) first. This leaves an and with a constant that
is harder to materialize.
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/test/CodeGen/RISCV/rv64zba.ll diff | blob | history
Domain: System / Toolchain;