radv: Optimize emitting prefetches
authorTuro Lamminen <turo.lamminen@alternativegames.net>
Tue, 24 Jan 2023 12:25:23 +0000 (14:25 +0200)
committerMarge Bot <emma+marge@anholt.net>
Fri, 27 Jan 2023 15:05:03 +0000 (15:05 +0000)
commitb2df787058be31484f2043bcc557892158078b23
tree6ebd2cf811eae0f91119298cd39fac9a049de617
parentbd78c8bbfa7dd3371215cf445bc9fe59e6ec296f
radv: Optimize emitting prefetches

Check the need for emitting prefetch before calling si_emit_cache_flush
to mask a possible cache miss delay and always inline radv_emit_prefetch_L2.
Either change alone is not significant but together they increase
drawcall throughput by 8% on i5-2500.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20877>
src/amd/vulkan/radv_cmd_buffer.c