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(parent: 27f2261) | patch
iio: dac: ad5791: Fix alignment for DMA saftey
authorJonathan Cameron <Jonathan.Cameron@huawei.com>
Sun, 8 May 2022 17:56:35 +0000 (18:56 +0100)
committerJonathan Cameron <Jonathan.Cameron@huawei.com>
Tue, 14 Jun 2022 10:53:16 +0000 (11:53 +0100)
commitb2d5e9de77c8774a5a6cff59d928f2fa38cbc642
treeb885cee2c0898a67d10a6652ca69c4a03ef51a11tree | snapshot
parent27f2261d16d01858b8e5baca5a1a515b040429c4commit | diff
iio: dac: ad5791: Fix alignment for DMA saftey

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: 791bb52a0cd2 ("iio:ad5791: Do not store transfer buffers on the stack")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-56-jic23@kernel.org
drivers/iio/dac/ad5791.c diff | blob | history
Domain: System / Kernel;