ARM: redo TTBR setup code for LPAE
authorRussell King <rmk+kernel@arm.linux.org.uk>
Sat, 4 Apr 2015 19:09:46 +0000 (20:09 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Mon, 1 Jun 2015 22:48:19 +0000 (23:48 +0100)
commitb2c3e38a54714e917c9e8675ff5812dca1c0f39d
tree0d5e9747b2c73ccd4c961c8d6a50841b52cf11fd
parent1221ed10f2a56ecdd8ff75f436f52aca5ba0f1d3
ARM: redo TTBR setup code for LPAE

Re-engineer the LPAE TTBR setup code.  Rather than passing some shifted
address in order to fit in a CPU register, pass either a full physical
address (in the case of r4, r5 for TTBR0) or a PFN (for TTBR1).

This removes the ARCH_PGD_SHIFT hack, and the last dangerous user of
cpu_set_ttbr() in the secondary CPU startup code path (which was there
to re-set TTBR1 to the appropriate high physical address space on
Keystone2.)

Tested-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/include/asm/memory.h
arch/arm/include/asm/proc-fns.h
arch/arm/include/asm/smp.h
arch/arm/kernel/head-nommu.S
arch/arm/kernel/head.S
arch/arm/kernel/smp.c
arch/arm/mach-keystone/platsmp.c
arch/arm/mm/proc-v7-2level.S
arch/arm/mm/proc-v7-3level.S
arch/arm/mm/proc-v7.S