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ARC: [plat-eznps] Use dedicated SMP barriers
authorNoam Camus <noamc@ezchip.com>
Fri, 10 Apr 2015 18:28:50 +0000 (21:28 +0300)
committerVineet Gupta <vgupta@synopsys.com>
Mon, 9 May 2016 04:02:33 +0000 (09:32 +0530)
commitb1f2f6f3cf5e37f0418f6cebf365cff7c3abf6d7
treed9a8d9d4d37ed7cbe7f098993c3856c756666d18tree | snapshot
parenta5a10d99a946602cf4ae50eadc65c2480dbd2e56commit | diff
ARC: [plat-eznps] Use dedicated SMP barriers

NPS device got 256 cores and each got 16 HW threads (SMT).
We use EZchip dedicated ISA to trigger HW scheduler of the
core that current HW thread belongs to.
This scheduling makes sure that data beyond barrier is available
to all HW threads in core and by that to all in device (4K).

Signed-off-by: Noam Camus <noamc@ezchip.com>
Cc: Peter Zijlstra <peterz@infradead.org>
arch/arc/include/asm/barrier.h diff | blob | history
Domain: System / Kernel;