author | ShihPo Hung <shihpo.hung@sifive.com> | |
Mon, 21 Dec 2020 06:41:47 +0000 (22:41 -0800) | ||
committer | ShihPo Hung <shihpo.hung@sifive.com> | |
Tue, 22 Dec 2020 01:37:20 +0000 (17:37 -0800) | ||
commit | b15ba2cf6fde9b7e8599dc9c5afc412a98aba5be | |
tree | 1e262ddd991c494a7232a4d7b588c4f14437957f | tree | snapshot |
parent | 6e2af4d6046995abf1003ebacfce95415010d574 | commit | diff |
llvm/include/llvm/IR/IntrinsicsRISCV.td | diff | blob | history | |
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | diff | blob | history | |
llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll | [new file with mode: 0644] | blob |
llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll | [new file with mode: 0644] | blob |