perf/x86: Fix exclusion of BTS and LBR for Goldmont
authorAndi Kleen <ak@linux.intel.com>
Fri, 9 Dec 2016 00:14:17 +0000 (16:14 -0800)
committerIngo Molnar <mingo@kernel.org>
Sun, 11 Dec 2016 12:06:09 +0000 (13:06 +0100)
commitb0c1ef52959582144bbea9a2b37db7f4c9e399f7
tree4e64446d543139c7177d08b9a060e2a340d3f400
parent6de75a37b8e82e3e6bbc773c1fbc7df8338efb90
perf/x86: Fix exclusion of BTS and LBR for Goldmont

An earlier patch allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: alexander.shishkin@intel.com
Cc: kan.liang@intel.com
Cc: <stable@vger.kernel.org>
Fixes: ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
Link: http://lkml.kernel.org/r/20161209001417.4713-1-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/events/core.c
arch/x86/events/perf_event.h