AMDGPU/MC: Refactor decoders. Rework decoders for float immediates

AMDGPU/MC: Refactor decoders. Rework decoders for float immediates

decodeFPImmed creates immediate operand using register operand width,
but size of created immediate should correspond to OperandType for
RegisterOperand.
e.g. OPW128 could be used for RegisterOperands that use v2f64 v4f32
and v8f16. Each RegisterOperands would have different OperandType and
require that immediate is decoded using 64, 32 and 16 bit immediate
respectively.
decodeOperand_<RegClass> only provides width for register decoding,
introduce decodeOperand_<RegClass>_Imm<ImmWidth> that also provides
width for immediate decoding.
Refactor RegisterOperands:
 - decoders get _Imm<ImmWidth> suffix in some cases
 - removed unused RegisterOperands defined via multiclass
 - use different RegisterOperand in a few places, new RegisterOperand's
   decoder corresponds to the number of bits used for operand's encoding
Refactor decoder functions:
 - add asserts for the size of encoding that will be decoded
 - regroup them according to the method of decoding
decodeOperand_<RegClass> (register only, no immediate) decoders can now
create immediate of consistent size, use it for better diagnostic of
'invalid immediate'.

Differential Revision: https://reviews.llvm.org/D142636