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(parent: 2cf12ae) | patch
[RISCV] Prevent assertion in the assembler if vmerge or vfmerge are given a V0 destin...
authorCraig Topper <craig.topper@sifive.com>
Tue, 15 Dec 2020 01:19:53 +0000 (17:19 -0800)
committerCraig Topper <craig.topper@sifive.com>
Tue, 15 Dec 2020 01:22:55 +0000 (17:22 -0800)
commitb094eaa392322a9a0073c84f0b6ea320d80dafcf
tree2719627173b498e3f441a4fb4e903cf7a1d7f2b0tree | snapshot
parent2cf12ae0cc3fd51b2708a2ee1f61d9e861ca6b9dcommit | diff
[RISCV] Prevent assertion in the assembler if vmerge or vfmerge are given a V0 destination.
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp diff | blob | history
llvm/test/MC/RISCV/rvv/invalid.s diff | blob | history
Domain: System / Toolchain;